Bug
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[EMCL-233] - "0x6502 Supported drive modes" register is missing CSV and CST modes
Improvement
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[EMCL-236] - Change Motor parameters default values
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[EMCL-240] - Modify register "Available phases mask" - 0x2FF0 / 0x2E
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[EMCL-264] - SinCos multiplier factor can be modified
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[EMCL-270] - Remove user polarity from "UART Enable GPO" feature
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[EMCL-294] - Set the Sync1 as synchronization signal instead of latch signal